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Cadence bestows VLSI design awards

Posted: 23 Nov 2010     Print Version  Bookmark and Share

Keywords:Cadence University Programme  Design Contest  VLSI design 

Cadence Design Systems (India) Pvt. Ltd declared the winners of its fifth annual Design Contest for Bachelor's and Master's level students from institutes that participate in the Cadence University Programme.

This year, the Cadence Design Contest received over 130 entries from 28 institutes that use Cadence technologies. The contest aims at fostering innovation and creativity among electronics engineering students in India, and encouraging them to address industry imperatives of System, SOC and Silicon Realisation.

The winners in the Bachelor's category are Aparna R, Arnold Pereira, Litesh Sajnani, Abishek Manian and Meera Shah from VESIT, Mumbai. The winning design titled "Implementation of High Speed Vedic Co-Processor Incorporated with a 32-bit Processor Executing RISC Instruction Set Architecture" includes applications such as signal processing; microprocessors and controllers; and astrology for fast computing of multiplication, division, and other algorithms.

"At the student-level we wanted to try to match the industry-level high-frequency processors and provide practical applications. We are trying to achieve a speed of 1GHz," says professor and guide of Vivekanand Educational Society's Institute of Technology (VESIT), Hardik Shah, whose team feels that the use of Cadence tools gave them a chance to work at industrial-level projects beyond their curriculum. Shah adds, "We need to spread the awareness that VLSI is the field for the future. Cadence's Design Contest allows us the opportunity to not only creatively apply our skills, but to also have our ideas reviewed by an eminent panel of industry leaders. This kind of real-world relevance is an excellent stepping-stone for students in a technical stream. "


VESIT-Mumbai winners (left to right): Aparna R, Arnold P, Hardik Shah (project guide), Litesh S, Abishek M, Meera S (not in photo)

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