Global Sources
EE Times-India
EE Times-India > EDA/IP

Xilinx employs stacked silicon tech for multi-FPGA

Posted: 03 Nov 2010     Print Version  Bookmark and Share

Keywords:stacked silicon  Moore's Law  interconnect technology  multi-FPGA 

Xilinx, Inc. has employed the stacked silicon interconnect technology to deliver multiple FPGA die in a single package for applications that require high-transistor and logic density, as well as tremendous levels of computational and bandwidth performance. The company promises that this enables 100x improvement in die-to-die bandwidth per watt and 2-3x capacity advantage over monolithic devices.

By embracing 3D packaging technologies and through-silicon vias (TSV) for its 28nm 7 series FPGAs, Xilinx's Targeted Design Platforms can address systems with resource requirements that are more than double the reach of the largest single-die FPGAs. This platform approach enables it to overcome the boundaries of Moore's Law and offer electronics manufacturers unparalleled power, bandwidth and density optimisation for the large-scale-integration of their systems, says Xilinx

"One of the ways the 28nm Xilinx 7 series FPGAs extend the range of applications programmable logic can address is by offering capacity of up to 2 million logic cells. Our stacked silicon interconnect packaging approach makes this remarkable achievement possible," said Vincent Tong, Xilinx senior VP. "Five years of Xilinx research and development coupled with industry leading technology from TSMC and our assembly suppliers has made possible our efforts to provide an innovative solution for enabling electronic systems developers to take the benefits of FPGAs further into their manufacturing flow."

With software support available in ISE Design Suite 13.1,which is currently available to beta customers, the 28nm Virtex-7 LX2000T device claims to be the world's first multi-die FPGA and provide more than 3.5X the logic capacity of the largest current-generation Xilinx 40nm FPGA with serial transceivers and 2.8X the logic capacity of the largest competing 28nm FPGA with serial transceivers. The device is made possible by micro-bump assembly, patented FPGA architectural innovations from Xilinx, and advanced technology from TSMC that deliver lower levels of power consumption, system cost and circuit board complexity compared to using multiple FPGAs, each in their own package, for the same application.

"Compared with traditional monolithic FPGAs, multi-chip packaging approach is an innovative way to deliver large-scale programmability with favourable yield, reliability, thermal gradient, and stress tolerance characteristics," said Shang-yi Chiang, senior VP of R&D at TSMC. "By using through-silicon via technology and silicon interposer to implement stacked silicon interconnect approach, Xilinx expects to reduce risks and is on the way to volume production with well-designed test vehicle runs that meet the company's criteria for design enablement, manufacturability validation, and reliability assessment."

1 • 2 Next Page Last Page

Comment on "Xilinx employs stacked silicon tech ..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top