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Analysis tool supports multi-core OCTEON processors

Posted: 17 Aug 2010     Print Version  Bookmark and Share

Keywords:embedded multi-core programming system  Prism  OCTEON  OCTEON II  Eclipse 

CriticalBlue reveals that its Prism software analysis, exploration and verification tool supports Cavium's multi-core (OCTEON and OCTEON II) processors.

Software developers building applications on multi-core OCTEON and OCTEON II processors can now use Prism, which can be downloaded from the CriticalBlue website. The Prism Core PSP for cnMIPS may now be used for free in a 30-day evaluation period.

Users may use the tool to quantify the benefits of software migration to the dual issue superscalar OCTEON and OCTEON II families. Users can analyse data cache misses and pipeline stalls on a thread, function or source line level, resulting in an ability to view the impact of such cache misses on the overall concurrent schedule. These can be done on an existing unmodified software application running on a single core model or development board. Experienced multi-core software programmers will benefit from Prism's capabilities in the area of performance tuning and multi-core software verification.

Prism is an Eclipse-based embedded multi-core programming system which allows software engineers to easily assess and realise the full potential of multi-core processors without significant changes to their development flow. It analyses the behaviour of code running on hardware development boards, virtual machines or simulators. It also permits engineers to take their existing sequential code, explore and analyse opportunities for concurrency before making any changes. Having identified optimal parallelisation strategies in this manner, developers can implement parallel structures, and use Prism again to verify performance efficiency and thread-safe operations.

The OCTEON family of Multi-Core MIPS64 processors from Cavium Networks is a scalable, high-performance, and low-power solution for intelligent networking applications ranging from 100Mbit/s to 40Gbit/s. These software-compatible processors—with 1 to 32 cnMIPS cores on a single chip, integrate next-generation networking I/Os along with an advanced security, storage, and application hardware acceleration—offer unprecedented throughput and programmability for the Layer 2 through Layer 7 processing requirements of intelligent networks, according to the Cavium.

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