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EMBC readies deep packet inspection specs

Posted: 05 Aug 2010     Print Version  Bookmark and Share

Keywords:deep packet inspection  network processor 

The Embedded Microprocessor Benchmarking Consortium (EMBC) has readied a draft for a benchmark in measuring the performance of deep packet inspection on network processors. The group hopes to have a specification completed by the end of the year.

A group of about a dozen network processor vendors and communications systems makers have been working on the so-called DPIbench for some time. The metric likely will report a system's throughput in bits per second while checking for a range of viruses and malware programs.

Embedded processors for communications systems used to just read a few bits on the headers of packets, such as its source and destination addresses. But the latest chips scan nearly every bit in a packet to determine the nature of its content, a job that can slow network throughput depending on how it is implemented in silicon and systems.

"The problem is today end users don't know what performance they will get," said Jeff Caldwell, R&D director at SonicWall and chairman of the DPIbench working group. "The DPIbench should provide the real numbers they can recognise on their networks," he said.

The effort is taking the SPECmark benchmark as a role model. DPIbench will not try to report the how well network processors stop a range of viruses and malware programs, just how much network throughput they deliver while checking packets.

The working group includes representatives from about a dozen companies including Cavium Networks, Intel, LSI and NetLogic as well as about four communications systems companies, most of which are choosing to remain anonymous so far.

"We would be very supportive of any benchmark that does a better job showing real world performance," said Ron Jankov, chief executive of NetLogic. "These days many vendors just report peak performance based on their data rates times the number of cores on their chips," he said.

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