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DAC panel debates 3D TSV future

Posted: 23 Jun 2010     Print Version  Bookmark and Share

Keywords:3D TSV  through-silicon-via  IC design  design flow 

A panel at the Design Automation Conference (DAC) debated on the roadmap for 3D through-silicon-via (TSV) interconnects and reached consensus that it will be awhile but inevitable that TSVs need to be phased in as a technology for obtaining performance levels needed by a host of applications.

"3D technology will hit the market in the next two to three years," said Pol Marchal, a principal scientist at IMEC. "The technology has great benefits for the three main application drivers of the semiconductor industry: convergence, high performance and memory systems."

Marchal said that IMEC has road maps for the design and technology challenges for each of the application domains. For the challenges to be met, "EDA must contribute an integrated design flow enabling the co-optimisation of chip and package design for signal integrity and power integrity, as well as mechanical/thermal integrity," said Marchal.

"3D IC integration using TSV interconnections is becoming a critical component to overcome the technology scaling barriers and low power requirements in mobile devices," said CAE researcher Myung-Soo Jang, of Samsung Electronics. In his presentation Jang showed an example of how with today's IC technology online video applications in 3D and mobile apps will require as much as 12.8GBit/s between I/O and memory. 3D packaging technology can eventually lower that frequency by as much as by 8X in Samsung DDRs.

LC Lu, director of TSV technologies at Taiwan Semiconductors Manufacturing Co., predicted that "3D IC/TSV is an industry trend gaining momentum due to the ever-converging alignment of the technology's benefits for 'More than Moore' SoC applications." Products using this technology will be rolled out in many different market segments.

TSMC recently extended its Open Innovation Platform with its Reference Flow 11.0 that emphasizes solutions provided by TSV technologies." Innovation is needed in good die sorting, multiple process variations, and thermal/mechanical stress," according to Lu.

"This is not a one size fits all applications type of technology", said Riko Radojcic, director of through silicon stacking initiatives at Qualcomm. "It is all about managing new choices when making the decision to go with TSV technology." Radojcic said that it is essential to implement a Path Finding process up front in the system design in order to explore design options and make the right choices related to technology, costs and die interactions.

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