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Overcome debugging challenges in DDR memory

Posted: 07 Jun 2010     Print Version  Bookmark and Share

Keywords:mixed signal oscilloscope  challenges MSO  high bandwidth oscilloscope 

DDR memory technology is the most common choice of memory devices found almost everywhere from computers, transportations, home entertainment systems to medical devices and consumer products. With the wide spread of the DDR usage, the new development and designs are pushing the requirement for higher performance and more power-efficient DDR memory devices.

New DDR technologies such as DDR3 (the third generation of DDR technology) and low-power DDR (LPDDR) technology devices are increasingly being considered in design because they offer these improved attributes.

You may think DDR memory designs are straightforward, but the higher data rates and lower voltage on these memory devices can quickly take away your design margins. Besides that, validating of the DDR interface is rapidly becoming a huge and complicated task.

Keep in mind that DDR interface is one of the most complex high speed interfaces because of the high pin count per memory device, and the high speed data transmission reaching the speed of serial technologies such as the USB 2.0 and PCIe technologies.

While the oscilloscope is widely used for performing physical layer validation on the DDR interface, the complexity of the DDR memory technology is making validation and debugging with a conventional oscilloscopes a challenge.

It probably limits you from further measurement capabilities such as command triggering, state machine decode and protocol debug. This article highlights a few of the challenges and how the use of a mixed-signal oscilloscope (MSO) can overcome these challenges (Figure 1).

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Figure 1: Analogue and logic channels on the MSO provide complex triggering, state machine decode and protocol measurements to allow power DDR validation and debug, beyond the capability of conventional oscilloscope.

Validation challenges
DDR memory technology is really a complex interface. Not only is the DDR interface made up of parallel, single-ended signals with a data transfer rate that is faster than the speed of a number serial technologies, the DDR interface also consists of a huge number of signal interconnects between the memory controller and the DDR chip.

On a typical DDR device, there are more than 20 signals, which consist of a clock, six control, 12 address, a strobe and eight data signals.

When initiating an operation, the memory controller would issue a command through its control signals to the DDR chip. A conventional oscilloscope, which consists of only four analog input channels, can be challenging to determine the type of commands sent over the DDR interface due to the limited channels.

The limited connection might also limit the triggering capability of the conventional oscilloscope for different commands since you probably need to connect to all six signals at the same time.

Even if you can deduce the command or state machine based on the limited control signals, you might still end up with the hassle of going back to the truth table on the DDR specification to hand decode the current command based on the high or low state of each control signals.

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