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No innovation wall for 25nm MLC NAND

Posted: 05 Apr 2010     Print Version  Bookmark and Share

Keywords:25nm NAND teardown  NAND flash  solid-state drive 

While most pundits have speculated that NAND has hit the wall, IM Flash Technologies (IMFT) continued their aggressive path scaling with the 25nm 8Gbyte, 2bit/cell multi-level cell (MLC) NAND and may even get one more node at 18 nm. On the scaling front, it's clear that IMFT is following 0.7x scaling every 12-15 months, which translates to almost 0.97x scaling compared with the logic technology time scale.

The IMFT 25nm die has an impressive foot print of 162 mm², one-sided pad layout, 79 per cent memory area efficiency (vs. die area) and is packaged in 48-pin lead-free TSOP. Another significant gain is double the memory capacity compared with the 4Gbyte (32Gbit) 34nm 2bit/cell MLC NAND die at approximately same die size. This may not cut the NAND flash or solid-state drive (SSD) price by half but it's something the SSD manufacturers would cheer about. The die is divided into two 32-Gb planes used in single or dual-plane operation. The bitline access and page buffers are placed in the centre of the die dividing the bitlines into half. This helps reduce the bitline capacitance and improves charging and discharging time.

For the first time, IMFT has successfully fabricated a 2xnm node 8Gbyte 2bit-per cell NAND flash using floating-gate cell technology. (Click on image to enlarge.)

NAND array overhead, (calculated as a ratio of overhead length to the total length of NAND string) stands at 14 per cent for the current IMFT 25nm 66-cell NAND string, compared with 23 per cent overhead for the 33-cell NAND string used at 34nm. That means the voltage controllers have to be dedicated for edge cells and the control circuitry have to work smarter and switch faster. In order to balance between the edge wordline effects and providing a cost-effective die size, the cell 0 and cell 65 are most likely one bit-per cell. The other alternative would have been to use a 67-cell string and use the edge cells as dummy wordlines, which would increase the die size.

IMFT was first to release 3xnm node followed by their recent announcement of 2xnm node. IMFT strategy seems to be more towards the node shrink first and then 3bit-per cell. Samsung and Toshiba slowly but surely are working towards 2xnm node, while Hynix may announce their 2xnm node in Q3 10. The choice between 3bit-per cell (higher density/low cost) and 2bit-per cell (lower density/more reliable) depends on whether the device is used for portable, cheaper storage (USB) or SSD market. Much remains to be seen what happens at the end of the year 2011.

Scaling challenges
The key for successful product roll out depends on how well the front-end-of-the-line process technologies like immersion lithography, self-aligned-double-patterning (SADP), self-aligned poly process, narrow shallow trench isolation (STI) gap fill, and air-gap isolation are integrated with each other. IMFT have used these technologies to successfully solve the physical, electrical, and reliability scaling challenges. The Process Analysis group at UBM TechInsights has recently analysed the IMFT's 25nm device to gain deeper understanding of the process technologies used.


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