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Debugging hardware tool packs 4Gb trace memory

Posted: 22 Mar 2010     Print Version  Bookmark and Share

Keywords:hardware tool  debugging  microcontroller  multi-core 

UAD3+

Programmierbare Logik & Systeme (pls) rolls out the Universal Access Device 3+ (UAD3+) hardware tool optimised for use in multi-core and multi-target systems with high clock frequencies.

The UAD3+ targets high-end trace, multi-core and multi-target debugging, profiling and calibration targeted for users of complex 16-and 32bit microcontrollers. With flexible pod and connector designs, up to eight cores and targets can be controlled with different debug protocols.

JTAG extender technology permits connection lengths of up to 5m to the base unit. Optional extenders are available with galvanic electrical isolation. The pods can also be used for CAN interface or logic analyser probe.

Targets can be accessed at speeds up to 100MHz clock frequency via serial interfaces such as JTAG, Device Access Port (DAP) or Serial Wire Debug (SWD).

During debugging, several core/targets can be synchronised by the UAD3+. Two input voltage ranges—1.6V to 5.5V standard or optionally 0.8V to 3.3V—cover all possible applications.

According to the company, the UAD3+ sets new standards in multi-core/multi-target debugging, and also in high-end real-time trace. The highly flexible pod and connector designs ensure simple and efficient support of trace protocols such as CoreSight ETM, Nexus, or OCDS LII. The distance between the trace pod on the target and the base unit may be up to 5m.

The UAD3+ has a trace memory of up to 4GBs, a maximal trace stream width of 32bits, and trace signals up to 500MHz.

Control of the UAD3+ is via the company's Universal Debug Engine (UAD) 2.7, which offers numerous functions for system visualisation such as trace window, applications profiling, and code coverage. Gigabit Ethernet, USB 2.0 or FireWire 800 interfaces are available as connections to the host PC.

The modular concept of the UAD3+ enables simple expansion to other architectures and debug protocols. Series production is planned for the second quarter of 2010.

- Toni McConnel
Embedded.com





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