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EE Times-India > EDA/IP

FPGA debug tool cuts design time by 50%

Posted: 03 Mar 2010     Print Version  Bookmark and Share

Keywords:FPGA  debug tool  bug fix  software 

GateRocket Inc. has released the latest version of its RocketVision debugging software that reduce overall design bring-up time by 50 per cent or more compared with traditional approaches by enabling engineers to find and fix bugs faster and avoid unnecessary re-runs of synthesis-to-place-and-route iterations.

The new features allow designers to select individual design blocks to run in their simulator or GateRocket's RocketDrive hardware verification system.

RocketVision 5.0 adds a new SoftPatch feature allows engineers to try a "soft" RTL fix to the FPGA without rerunning synthesis and place-and-route. The SoftPatch feature enables users to sequence through each bug and test fixes without re-building the FPGA, eliminating hours of tedious work (weeks or months over the course of a project), according to the company.

The new version of RocketVision also includes an enhanced AutoCompare features that helps identify bugs at the block or full chip level, GateRocket said. It allows designers to automatically compare the signals between the RTL and hardware representations of the complete FPGA design and highlights any differences that occur, simplifying the debugging process and helping to quickly identify the location of each divergence, the company said.

Both the latest versions of RocketDrive and RocketVision now support 64bit versions of the industry's most popular simulators from Mentor Graphics Corp., Cadence Design Systems Inc. and Synopsys Inc., GateRocket said.

RocketVision 5.0 is a RocketDrive option and is available immediately with a starting price of $9,500, the company said.

- EE Times

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