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Design, accuracy and calibration of ADCs on the MPC5500 family

Posted: 12 Feb 2010     Print Version  Bookmark and Share

Keywords:ADC calibration  ADC design  MPC5500 ADC design 

A new architecture of the ADC is introduced with the MPC5554 device to meet requirements of increased speed and accuracy. This architecture consists of a converter engine with improved linearity and correction hardware to remove linear gain and offset errors. This correction hardware is the ADC calibration sub-system.

This application note outlines the advantages of the new redundant signed digit (RSD) architecture of the ADC introduced with the MPC5554, compared to the successive approximation architecture used in the MPC500 family. It discusses the gain and offset errors introduced by the RSD ADC and how the hardware multiply accumulate (MAC) unit is used to remove them. The ADC design features used to recover full range are explained along with design features in the MAC required to avoid lost codes, and the half-count offset adder that increases accuracy. Levels of calibration and their resulting accuracy are described. The parameters affecting total error are also discussed.

View the PDF document for more information.

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