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Towards a more efficient packet processing (Part 1)

Posted: 09 Feb 2010     Print Version  Bookmark and Share

Keywords:efficient packet processing  multicore processors  GPIO 

With the advent of the latest generation of multicore processors, it has become feasible from the performance as well as from the power consumption point of view to build complete packet processing applications using general purpose architecture processors, rather than dedicated ASIC and ASSP SoCs.

Architects and developers in the industry are now considering these processors as an attractive choice for implementing a wide range of networking applications, as performance levels that could previously be obtained only with network processors (NPUs) or ASICs can now also be achieved with multi-core architecture processors, but without incurring the disadvantages of the former.

View the PDF document for more information.





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