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Canon India centre taps Mentor OVM platform

Posted: 13 Jan 2010     Print Version  Bookmark and Share

Keywords:OVM  design centre  verification platform 

Mentor Graphics Corp. declared that the Canon India Design Centre has successfully deployed the Questa advanced verification platform with SystemVerilog as a next-generation HVL and Open Verification Methodology (OVM)—based verification environment.

The Canon India design centre chose the Questa advanced verification platform, combined with the OVM, to ensure the highest level of modularity, productivity and reuse for the verification of Canon India's complex and highly compute-intensive integrated circuit (IC) designs. In particular, the Canon India design centre verification team used SystemVerilog with OVM for verifying multi-layered communication IP.

"The OVM defines the concept of 'object oriented' for verification environment in a systematic way," said Sunil Kashide, verification head at the Canon India design centre. "We were able to define and build the verification architecture much more robust and modular. Mentor India has given extensive support in understanding and exercising the different concepts. With OVM, we could reduce the overall timeline by bringing parallelism into execution."

"Mentor Graphics' team has provided us extended support during the evaluation phase," said Dhanaji Kamble, Design Centre head. "We could successfully build the domain expertise and boost team confidence for the next-generation verification methodology."

"The OVM was developed to deliver ready-to-use, reusable, and scalable testbench components within a proven, repeatable methodology," said John Lenyo, general manager of Mentor's Functional Verification division. "The combination of industry-leading SystemVerilog support and OVM-specific debug capabilities in the Questa functional verification environment has helped customers like Canon India quickly get successful results in real projects."

Open Verification Methodology (OVM)
The OVM is based on the IEEE 1800 SystemVerilog standard and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP. The methodology is non-vendor specific and is interoperable with multiple languages and simulators. The OVM is fully open and includes a robust class library and source code that is available for download.

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