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Clock generator with -57dBc PSNR lowers jitter degradation

Posted: 22 Dec 2009     Print Version  Bookmark and Share

Keywords:clock generator  Ethernet  Fibre Channel 

MAX3625B clock generator

MAX3625B high-performance, three-output clock generator from Maxim is designed for Ethernet and Fibre Channel equipment. The device utilises a low-noise VCO and PLL architecture to generate a high-frequency, ultra-low-jitter (0.36psRMS) clock signal from a low-frequency crystal resonator or reference clock input. Its -57dBc PSNR minimises jitter degradation and eases design in noisy system environments.

The MAX3625B eliminates the expensive crystal oscillator and fanout buffer required by conventional solutions, as it only requires an external, AT-cut fundamental-mode crystal. Because it reduces the space requirements and cost of the total clock-distribution solution, this device is well suited for applications such as Ethernet switches/routers and storage-area network switches.

To further reduce the overall BOM, the MAX3625B provides three LVPECL outputs up to 320MHz from two output-divider banks. The output dividers are programmable, allowing designers to set these outputs to the frequencies required by their application.

The MAX3625B operates from 3.3V ±5 per cent and is fully specified over the -40°C to +85°C extended temperature range. It is available in a 7.8mm x 4.4mm, Pb-free, 24-pin TSSOP package. Prices start at Rs. 343.55 ($7.35) (1,000-up, FOB USA).





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