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Simulation debugging using triple speed Ethernet testbench

Posted: 18 Dec 2009     Print Version  Bookmark and Share

Keywords:debugging simulation  Ethernet testbench  system debug 

This application note shows how you can leverage the verification environment in the testbench provided in the Altera Triple Speed Ethernet MegaCore function to debug your system design. You can use the different types of loopback in the testbench to simulate your system design, and create various common scenarios by configuring the parameters and the state machine in the testbench.

The Triple Speed Ethernet MegaCore function consists of a 10/100/1,000Mbit/s Ethernet media access controller (MAC), a 1000BASE-X physical coding sub-layer (PCS), and an optional physical medium attachment (PMA). The Triple Speed Ethernet MegaCore function supports interface to commercial Ethernet PHY devices via medium independent interface (MII) and gigabit medium independent interface (GMII). The MegaCore function also supports reduced gigabit medium independent interface (RGMII) in 10/100/1,000Mbit/s.

The Triple Speed Ethernet MegaCore function provides a testbench that supports simulation of all basic Ethernet packet transactions, and has an easy-to-use simulation environment for any standard HDL simulator. The testbench consists of device under test (DUT) modules that are the custom MegaCore function variations, the Ethernet frame generators, and clock and reset generators.

The testbench is intended for simulating common configurations and may not cover all the possible configurations of the Triple Speed Ethernet MegaCore function.

View the PDF document for more information.

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