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Distributed processing blocks boost processor efficiency

Posted: 02 Dec 2009     Print Version  Bookmark and Share

Keywords:processor efficiency  processing blocks  mini processors 

In the past few years, we have seen multi-processing systems become more mainstream. In fact, most modern personal computer CPU's now feature symmetric multi-processing systems (SMP), where multiple instantiations of the same processor share the processing burden of the applications running on the PC.

While SMP's are quite common today, we typically have not seen a shift towards multi-processing in embedded computing. However, a new type of embedded design technique gives engineers the freedom to intelligently distribute processing functions across a digital sub-system.

This article looks at an example of the distributed processing technique using Cypress Semiconductor's PSoC 3 and PSoC 5 architectures, which consist of a main CPU (in this case an 8051 or ARM Cortex M3), a DMA engine and array of Universal Digital Blocks (UDB).

The UDBs effectively serve as an array of mini-processors. By distributing processing functions across such a sub-system, the engineer can increase the efficiency of the overall system by offloading less computationally complex processing functions.

There are multiple benefits to breaking up processing functions across multiple functional blocks, the largest of which is a reduction in active power consumption. By lowering the burden on the CPU of processing MIPS-hungry—but computationally simple functions such servicing interrupts—it is possible to run the application at a lower frequency since the CPU does not have to burn instruction cycles on the less complex functions in addition to all of the functions in the application.

This reduces the power consumption of the overall applications in two ways. The first benefit is obvious—by reducing the CPU clock, you see a linear decrease in active power consumption as the clock speed is reduced.

The second benefit, while perhaps more subtle, is equally important: The CPU has roughly 10x more logic gates than the UDB.

In addition to significantly reducing active power consumption in application, another benefit of distributed processing is that the CPU is free from the burden of the more mundane processing. It can then focus its MIPS on functions that better take advantage of the features of the CPU, such as more computationally intensive functions like multiply and divide instructions.

To understand how it is possible to break up the processing functions across the architecture, we will take a look at a common embedded application as an example, brushless DC motor control. But first let's take a look under the hood, and examine the PSoC 3/PSoC 5 digital sub-system to understand its capabilities.

View the PDF document for more information.

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