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EE Times-India > EDA/IP

Cadence, ARM team up for SoC design

Posted: 23 Oct 2009     Print Version  Bookmark and Share

Keywords:Cadence ARM collaboration  design flow  EDA 

Cadence Design Systems Inc. has entered into a strategic collaboration with ARM Ltd for the creation of a next-generation SoC design flow. They seek to accelerate time to market and lower the cost of SoC integration and verification by combining the Cadence Chip Planning System and Cadence Incisive functional verification solutions with the ARM AMBA Designer, Performance Exploration tools and Network Interconnect IP.

"Both ARM and Cadence have developed techniques to give our mutual customers better methods to optimise SoC integration architectures and IP selection, and provide VIP-based automation to speed both performance and functional verification time," said Steve Glaser, corporate VP, strategy and planning at Cadence. "With the evolution of ever-more complex multimedia and multi-processor SoCs, there is a compelling need to find new ways to specify, optimise and verify both the performance and functionality of the SoC interconnect and the full SoC assembly."

"ARM and Cadence expect our customers to achieve major efficiency savings through the integration of both AMBA system IP and associated Cadence and AMBA design tools," said Michael Dimelow, director of marketing at ARM. "Early estimation of the power and cost of selected IP components enables customers to perform 'what if' calculations to optimise their SoC architectures. Generated traffic profiles from AMBA VPE rapidly tune the AMBA network interconnect performance, and Cadence metric-driven verification IP ensures functional integrity of the integrated IP at the SoC level."

The companies plan to deliver increasingly integrated solutions to joint customers in multiple phases through 2010.

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