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Camera IP core packs bad pixel detection

Posted: 15 Oct 2009     Print Version  Bookmark and Share

Keywords:camera  processor  IP core  sensor 

Silicon Image Inc. grows its family of cameraIC camera processor cores. The camerIC-18 core offers 18 megapixel (MP) image signal processing (ISP) technology and suits integration into DSC and video SoC application processors for cell phones, portable multimedia players (PMPs) and netbooks.

Silicon Image's family of camerIC IP cores offers a cost-effective and power efficient design while placing high-performance DSC features in the hands of mobile device users. The camerIC-18 supports resolutions ranging from 5Mpixel to 18Mpixel, all in a single low-cost/low-power design.

To effectively deliver resolutions above 12Mpixel, the camerIC-18 IP core now includes sophisticated bad pixel detection/correction and noise reduction techniques to ensure image quality even when combined with the lower cost, high-resolution CMOS sensors commonly found in mobile devices. The camerIC-18 IP core also supports wide dynamic range processing and digital image stabilisation along with an extensive set of standard features including lens shade correction, auto focus measurement, auto white balance and auto exposure support by brightness measurement.

By 2013, over 95 per cent of mobile phones will have an integrated digital camera, and by 2013, over 25 per cent of smart phones will support 5MP or higher resolution cameras.

"Mobile phone cameras of increasing resolution are becoming pervasive throughout the market," said Will Strauss, principal analyst with Forward Concepts. "It's just a matter of time before the feature sets commonly found in DSCs will be integrated into mobile devices and the camerIC-18 camera processor intends to accelerate this market transition."

Traditionally, ISP technologies have been integrated into the CMOS sensor or separate application processor semiconductors. However, for resolutions at 5MP and higher, there are increased costs and inherent technical challenges associated with incorporating ISPs into the CMOS sensor. As mobile devices use smaller foundry processes, the growing trend is for ISP technologies to be integrated into the SoC in an effort to further reduce the cost and power consumption of mobile devices.

"Since 2002, Silicon Image has led the market in delivering cost-effective, low-power camera processor designs for use in mobile applications," said Ron Richter, director of business development at Silicon Image Inc. "The camerIC-18 IP core continues this tradition by providing mobile SoC developers with market leading digital still camera and camcorder capabilities and flexibility in choosing CMOS sensor suppliers."

The camerIC-18 IP core has the imaging bandwidth to support high-definition, 3D, 4K and higher resolution video camcorder ISP functions. A 4K resolution camcorder design incorporating a camerIC-18 IP core and running at 30fps will only require about 700k gates to be implemented in hardware and consumes as little as 125mW of power. Only 30 MIPS of CPU time are required to support this hardware design, making the camerIC-18 IP core one of the industry's highest performing, lowest cost, lowest power consumption camera processors in the world.

Silicon Image's family of IP cores also includes a broad range of HDMI technology solutions, including transmitters and receivers incorporating HDMI Specification Version 1.4 features, Mobile High-Definition Link technology, serial ATA storage, and high-definition MPEG/H.264/VC-1 video decoder applications.

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