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Hurdling 45nm software-to-silicon verification problems

Posted: 10 Aug 2009     Print Version  Bookmark and Share

Keywords:45nm  verification problems  embedded chip development 

Chip and system developers once considered verification as a secondary activity following the main challenge of design, with the "Designer" playing the central role in a design's success. This notion is firmly turned on its head today, as verification is the biggest component of chip hardware development budgets, schedules, staffing and risk.

With verification complexity growing faster than Moore's Law, compounded by increasing mixed-signal content and advanced low-power design techniques, the importance of verification in the chip hardware development process is certain to increase. In fact, venture capitalists have started focusing on verification costs as a factor in determining which chip startups to fund. Similarly, embedded software used to be a minor or non-existent deliverable for typical semiconductor devices. At 45nm and beyond, software accounts for a full 60 percent of total chip development cost, with major implications on how chips and systems are verified. It is no surprise, then, that the International Technology Roadmap for Semiconductors predicts that, "Without major breakthroughs, verification will be a non-scalable, show-stopping barrier to further progress in the semiconductor industry."

The growing role of verification complexity and embedded software in the chip-development process presents many challenges to tool vendors and system designers alike. The four areas that vendors and designers must focus on to address key software-to-silicon verification challenges are the following: verification efficiency; verification performance; early software development; and cross-domain verification.

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