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Soitec, IBM push 22nm for 3D ICs

Posted: 16 Jul 2009     Print Version  Bookmark and Share

Keywords:22nm  3D  silicon-on-insulator 

Silicon-on-insulator (SOI) supplier Soitec Group and IBM Corp. have partnered to pioneer 22nm node and beyond silicon wafer substrate and bonding techniques that will enable wafer-level, 3D integration technology for next-generation ICs. The two companies have been working together for many years to improve the design and specifications of advanced silicon wafer substrates to meet the needs of IBM's manufacturing roadmap.

The collaboration is developing highly flexible and cost-effective solutions for wafer-to-wafer stacking. Such technology is expected to yield ICs with faster speeds and higher performance. Soitec will leverage its Smart Stacking technology and all of its wafer-level bonding expertise including oxide-to-oxide and metal-to-metal molecular bonding—developed in collaboration with the Electronics and Information Technology Laboratory of the of the French Atomic Energy Commission.

"This collaboration with Soitec is another step in IBM's drive to accelerate 3D integration technology, and reinforces the expanding IBM ecosystem of leading companies and research organisations that are working together to achieve significant advances in semiconductor and packaging technology," said Gary Patton, VP of the semiconductor research and development centre of IBM. "Through these collaborations, IBM intends to accelerate the development of emerging 3D integration technology and demonstrate the possibilities of achieving higher circuit densities, faster speeds and lower power usage with this vertical integration approach."

"Soitec has continuously supported IBM's development programs over the past 15 years with our SOI and other engineered substrates. We expect this new collaboration with IBM will help solve the challenges that IBM is addressing through its 3D program," said Carlos Mazuré, chief technology officer of Soitec.

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