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EE Times-India > EDA/IP

Team-up enables MEMS/IC co-design, co-verification

Posted: 20 May 2009     Print Version  Bookmark and Share

Keywords:CMOS  MEMS+IC  3-D CAD  IC design 

MEMS+IC, by contrast, lets the MEMS designers work in the 3-D CAD environment with which they are familiar, then automatically transfers a fully parameterised behavioural model of the design into the IC design and simulation environment offered by Cadence's Virtuoso tool.

"We see the MEMS trend going the same way we saw analogue and digital going. They used to be fairly decoupled, then you started to see digital methods distinctly built into analogue functions," said Randolph Fish, director of product marketing for Virtuoso. "Now we are seeing the same thing in the MEMS world. At first the MEMS element was fairly decoupled from its electronics, but that's no longer true; the functionality of a MEMS component itself is now dependent upon the [electronic] component."

The Cadence Connections programme already supports a MEMS add-on for Virtuoso from SoftMEMS LLC, but that solution does not let the MEMS design team use the 3-D modelling tools with which they are already familiar. MEMS+, on the other hand, uses traditional 3-D modelling views to create MEMS models that automatically translate to the Virtuoso EDA environment.

"We wanted to partner with somebody who was committed to MEMS and [was] considered a leader there," said Fish. "That's how we got to Coventor."

IC designers can work in Virtuoso with the MEMS device using the same methods used for any other digital, analogue or mixed-signal device, including all manufacturing variables describing material properties, dimensional parameters and geometric properties of the combined design that allow accurate estimations of performance and yield.

The MEMS engineering team automatically generates a netlist for its completed design, which appears as a MEMS symbol in the Virtuoso Schematic Editor. The IC designer can then add the electronic elements to the design and run co-simulations of the MEMS and IC elements at the same time using the same simulator (either Spectre or UltraSim), which is connected to the MEMS+ component library. After co-simulation, the MEMS engineers can also review the results in MEMS+, including complete 3-D animation of the MEMS device's mechanical behaviours. When both teams are happy with the design, a parameterised layout cell can be exported to generate the final layout of the completed device for the foundry.

The Coventor design team is working to integrate the MEMS+ tool with other design environments besides Cadence's Virtuoso. The next implementation will offer integration with Matlab's Simulink, Coventor said.

-R. Colin Johnson
EE Times

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