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AES IP cores available on Speedster FPGAs

Posted: 12 May 2009     Print Version  Bookmark and Share

Keywords:Speedster FPGA  IP cores  ASIC  encryption algorithm 

The Speedster FPGAs from Achronix Semiconductor Corp. are now available with a series of Advanced Encryption Standard IP cores developed with Signali Corp.

The cores are targeted at 10-, 40- and 100-Gbps applications. The 128-bit key size AES cores are designed for use in high-performance applications such as Gigabit-capable Passive Optical Networks.

The Speedster chips, launched in September 2008 and offering three times the performance of conventional FPGAs, targets traditional ASIC applications requiring high data throughput. Many of these also require increasingly sophisticated encryption algorithms to thwart hacking attempts from around the globe.

In order to achieve the performance and resource utilisation targets, Signali implemented two configurations for the AES IP cores: a 16-bit core, aimed at 10-Gbps applications, features a pin-efficient 16-bit data path while a second, 128-bit data path core, targets 40- to 100-Gbps applications. Both cores use 128-bit keys and operate in CTR (counter) mode, designed for use in high-performance applications such as GPON. The cores are provided in standard Verilog or VHDL RTL, together with simulation models, test benches and complete documentation.

Signali uses its Quattro technology to transform high-level descriptions of data-intensive functions, such as AES, automatically into RTL. These tools allow very rapid algorithm and microarchitecture exploration at the design level, allowing the Signali's designers to quickly choose the best solution for specific implementation platforms. Quattro enabled Signali's engineers to maximise usage of the capabilities of the Achronix Speedster FPGA architecture.

"Signali's implementation with Achronix high performance FPGAs deliver peace of mind to system engineers while striking the right balance between resource allocation and performance," said Ali Burney, SerDes and IP marketing manager for Achronix, in a statement.

"Our expertise in design and implementation of computationally efficient, complex algorithms, coupled with our innovative development methodology, enabled Signali to quickly explore many different microarchitectures during our development work to find the one ideally suited for deployment on Achronix' Speedster," said Mark Konopacky, responsible for business development for Signali, in the same statement.

-Peter Clarke
EE Times Europe

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