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Guide to DisplayPort PCB layout

Posted: 28 Apr 2009     Print Version  Bookmark and Share

Keywords:DisplayPort  PTN33xx  CBTL061xx 

This document by NXP provides a practical guideline for incorporating the DisplayPort (DP) ICs, DisplayPort level shifter PTN33xx family and DP/PCI Express multiplexer CBTL061xx family, layout into a printed circuit board design.

DisplayPort interconnect is a point-to-point layout of serial differential signal trace pairs. The document provides guidelines for DP lane connection for the PCB traces, vias and AC coupling capacitors. The most important considerations are to minimise loss and jitter, and to maintain signal integrity.

These are general guidelines only. Board designers should carefully weigh design trade-offs and use simulation analysis to ensure a successful implementation.

DisplayPort is a scalable digital display interface. The interface is designed to support both internal chip-to-chip and external box-to-box digital display connections. The Main Link consists of one, two or four AC-coupled, doubly terminated differential pairs (lanes). Two link rates are supported: 2.7Gbps and 1.62Gbps per lane.

View the PDF document for more information.

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