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IMEC sends DFM tool for embedded SRAMs to Samsung

Posted: 23 Apr 2009     Print Version  Bookmark and Share

Keywords:EDA tool  embedded SRAM  process variations  design-for-manufacturing 

IMEC announced that it has successfully transferred the first EDA tool for statistical memory analysis to Samsung Electronics. The Memory Variability Aware Modelling (MemoryVAM) predicts yield loss of SRAMs caused by the process variations of deep-sub-micron IC technologies.

IMEC's MemoryVAM is an essential tool to avoid already at design time the most likely reasons for failure, anticipating and correcting weak design spots before tape-out, and hence avoiding redesign spins after processing. The tool also provides key help to memory and system designers to estimate yield loss due to changes of for example cycle time, access time and power consumption (static/dynamic) caused by process variations.

"With MemoryVAM, IMEC completes a missing steppingstone in industrial and academic state-of-the-art Design-For-Manufacturing flows which lacked such modelling capabilities for memories;" said Rudy Lauwereins, Vice President Smart Systems Technology Office at IMEC.

"We expect that MemoryVAM will be helpful for parametric yield modelling of embedded SRAM design and for understanding the unknown gap between design and silicon results due to process variability in deep subµm technology below 45nm," said Kyu-Myung Choi, Vice President of Design Technology Team at Samsung Electronics.

MemoryVAM is part of IMEC's Variability Aware Modelling (VAM) flow which is the first holistic flow capable of percolating process variations all the way from the process technology up to the SoC level. VAM enables to track the reasons for yield loss and the relative likelihood of such failure. Unlike most of the statistical analysis techniques, VAM is unique in its kind by accurately keeping track of all statistical process, design and environmental correlations tightly linked together and across abstraction levels.

MemoryVAM builds on IMEC's revolutionary method to analyse performance metrics of semiconductor memories under process variations. The method requires mainly three input items. The first is a transistor level netlist description of a segment of the memory describing all circuitry involved from input to output. The second one is a set of parameters describing the internal architecture of the memory, thus how the memory is built from the segment information, including redundancy and error correction code infrastructure. The third one is information about the variability of the devices and interconnects used in the underlying technology. This information can be provided in either the form of statistical distributions of certain transistor parameters, scattered data obtained via statistical simulation of the device or just plain data set obtained via silicon measurements.

The power of MemoryVAM lies in the analysis of parameters of the memory that can be directly embedded in the input netlist by the designer. These are then used to carry out the implementation of the method, without requiring additional custom modelling steps from the user. The key to this strategy is the ability to complement the analysis of a nominal memory model under test with statistically sampled variants of the devices. This is done by using an in-house developed statistically enhanced Monte Carlo technique, although it also allows the usage of any other available enhanced sampling technique.

With this novel and fast analytical technique, statistical information on the critical path percolates to the complete SRAM organisation level, resulting in a realistic prediction of the yield as perceived by the memory tester and/or equivalent built-in-self-testing (BIST) technique.

Find out more on memory technology! Visit Embedded Design India.

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