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EE Times-India > EDA/IP

Implement PCIe on FPGA with interface wrapper

Posted: 14 Apr 2009     Print Version  Bookmark and Share

Keywords:FPGA  PCI Express  SerDes 

Many end-applications today employ an FPGA-based design as an inherent component of their solution. They often require PCI Express (PCIe) as an indispensible feature, to provide a standardised interface with other components in the system.

Historically, PCIe has been difficult to implement in FPGA because it requires multi-gigabit SerDes and analogue circuitry with stringent electrical requirements.

Additionally, PCI Express implementations requires complex digital logic including Physical, Data Link and Transaction layers with large data paths running at high frequency, thus making it difficult to implement in FPGA.

The most common methods used for implementing PCI Express in FPGAs include:
- ASSP/PCI Express bridge chip
- FPGA with digital controller soft-IP and built-in SerDes/PHY
- FPGA with digital controller soft-IP and external discrete PHY chip
- FPGA with built-in PCI Express hard-IP

Each solution has its pros and cons and this paper will explore the different approaches to help pinpoint the best solution for an application.

View the PDF document for more information.

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