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ASIC design starts drop 22% in '09

Posted: 01 Apr 2009     Print Version  Bookmark and Share

Keywords:ASIC  design starts  FPGAs 

FPGAs will further displace ASICs in 2009 due to the global economic crisis, with the former currently having a 30-to-one edge in design starts, according to Gartner, Inc. ASIC design starts are expected to fall by 22 per cent this year as companies are compelled push out or cancel designs.

ASIC design starts—completed designs that have taped out—fell 9.5 per cent in 2008, reported Gartner. The firm said the financial crisis started to take its toll on ASIC design starts in the fourth quarter of 2008 in the form of push-outs of design projects into 2009.

Since most ASIC vendors have a design cancel fee, there will likely be no word of them being cancelled, Gartner said. But just how many of these designs will never go forward is a key question, the firm said.

"More likely, we will see a large percentage of these questionable designs not hit any production and die a slow death by indefinite push-outs," wrote Gartner analyst Bryan Lewis in a report dated March 30.

New ASIC design starts have been dropping in numbers for years due to system integration, rising design costs and other types of devices, such as FPGAs or ASSPs, taking the socket, Gartner said.

At a product launch event in February, Xilinx, Inc. president and CEO Moshe Gavrielov presented data on the trend of declining ASIC starts. Gavrielov spoke of a "programmable imperative," when, he said, FPGAs will dominate for many applications while traditional gate arrays and structured arrays are relegated to high-volume tasks.

Gavrielov argued that factors such as the technological evolution of the FPGA and economic factors such as the rising cost of photomasks make FPGAs the attractive choice for all but the most high-volume applications.

- Dylan McGrath
EE Times

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