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Close timing on high-speed ADCs

Posted: 24 Mar 2009     Print Version  Bookmark and Share

Keywords:analogue-to-digital converters  bit resolution 

High-speed, high-resolution analogue-to-digital converters (ADCs) have become roaring fast in the recent years. It was only in 2006 when a state-of-the-art, 12-bit converter reached 250 megasamples/sec (MSPS). Fast forward to today and the speed has doubled to 500MSPS. Similar trends are becoming apparent at the 14- and 16-bit resolutions. This suggests that given a bit resolution, the ADC speed is also doubling nearly every two years. As a consequence of the sampling rates, it is becoming increasingly important to close digital timing to ensure data integrity of your end system.

To close timing, locate the setup time (tsu) and hold time (th) in both the ADC and digital receiver's datasheets. Setup time is when the data must be valid before the receiver's clock edge, whereas hold time is the amount of time the ADC data must be valid after the clock edge. Adding an ADC's setup and hold time together determines the time data is valid. As a consequence, large setup and hold times is a desired condition for an ADC.

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