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Byte enable in standby mode for SRAMs

Posted: 20 Mar 2009     Print Version  Bookmark and Share

Keywords:byte enable pins  MoBL SRAMs  CMOS 

This document provides the recommended levels and usage of byte enable pins (BHE and BLE) when operated in standby mode for Cypress 90nm x16 MoBL SRAMs. The 90 nm MoBL SRAMs are targeted for use in low power battery operated applications.

To meet the ISB2 limit, the device should be disabled with CE high and all other inputs at the CMOS level > VCC – 0.2V or < 0.2V. However, in battery-backed systems, the SRAM is held in data retention mode by the battery with all its inputs, except CE, left floating. The inputs are left floating because the rest of the application circuit is powered down in this mode. In such applications, to ensure low standby power as specified in the data sheet, the byte enable pins BHE and BLE must be tied to VSS through pull down resistors, while all other inputs can be left floating.

View the PDF document for more information.

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