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Synopsys CEO says ICs will rebound

Posted: 19 Mar 2009     Print Version  Bookmark and Share

Keywords:silicon technologies  design tape-outs  engineering costs  verification complexity 

On the alarming rise in verification complexity and cost, de Geus presented data from the International Technology Roadmap for Semiconductors indicating that a 675 per cent increase in verification complexity is required over the next seven years.

De Geus' presentation referenced Synopsys' acquisitions over the past three years of Synplicity, Virtio Corp. and ProDesign's CHIPit business unit as evidence that Synopsys is investing in hardware-software co-verification technologies in order to facilitate system prototyping.

Synopsys' new products
De Geus detailed Lynx, an automated chip development environment recently introduced by the company. Lynx combines an RTL-to-GDSII design flow with productivity-enhancing features to accelerate chip development while mitigating the risks of designing at new process nodes. A Synopsys employee joined de Geus on stage to do a demo of the new tool.

In his presentation, de Geus also highlighted other recent Synopsys product innovations, including a 2-3X speed-up in design turnaround time from the latest release of IC Compiler, advancements in the Galaxy Implementation Platform, USB 3.0 IP cores and flexible multi-core processing technology in the latest release of the PrimeTime static timing analysis tool.

Elsewhere at the ISQED conference, Synopsys announced Yield Explorer, a new yield management tool said to expedite the discovery and mitigation of yield limiters in leading-edge integrated circuits.

- Dylan McGrath
EE Times

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