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EE Times-India > EDA/IP

IP devt, FPGA prototyping with SystemC/TLM

Posted: 18 Mar 2009     Print Version  Bookmark and Share

Keywords:Register Transfer Level  IPs  abstraction 

With the advent of SoC technology, designs are becoming bigger in size and thus highly complex, time-to-market is becoming critical, and at the same time, Register Transfer Level (RTL) methodologies are generally becoming insufficient to fit into this new role. These factors are driving designers to explore new methodologies for early verification of complex IPs (hardware as well as software) as well as complete system.

This article discusses a design flow that starts with highly abstracted models to cycle accurate or RTL models of IP. While moving to lower levels of abstraction, the modelling becomes complex and so does the verification of the IP. Our approach is suited to this scenario because it permits us to run same test benches/test scenarios in similar environments throughout, hence permitting the reuse of all the test cases and environments across the complete development cycle efficiently.

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