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Clock concurrent optimisation tool launched

Posted: 27 Feb 2009     Print Version  Bookmark and Share

Keywords:clock concurrent optimisation  clock tree synthesis  physical optimisation  chip speed 

Azuro, Inc. has introduced a new clock concurrent optimisation tool. Rubix uniquely combines the separate design flow steps of physical optimisation and clock tree synthesis (CTS) to deliver up to 20% increases in chip speed and dramatically slash chip time to market, says Azuro.

"Clock concurrent optimisation makes sense. Rubix plugged easily into our flow, and improved key chip speed metrics (WNS and TNS) out of the box on some of our toughest blocks, with no impact on area," said David Dumolin, director engineering at NVIDIA.

Physical optimisation is the step in the design flow which most influences chip speed, area, and power. But physical optimisation occurs before clocks are inserted into a design during the clock tree synthesis step and makes decisions based on an idealised, balanced model of clocks. At 65nm and below, this model has diverged dramatically from reality due to three key industry trends: design complexity, on-chip-variation, and low power.

This divergence directly impacts the validity of decisions made during physical optimisation, significantly degrading achievable chip speed and causing a dramatic spike in manual iterations in design flows. Clock concurrent optimisation addresses this divergence by building clocks during—rather than after—physical optimisation and therefore makes all decisions based on real clocks, not idealised clocks.

"Clock gating, on-chip variation, and an explosion in inter-clock timing complexity collectively cripple the ability of traditional physical optimisation tools to perform timing optimisation effectively," said Greg Buchner, former vice president engineering at ATI Technologies and AMD, and an advisor to Azuro. "Clock concurrent optimisation truly is something fresh and much needed by the chip design community."

Using an idealised, balanced model of clocking, the time available for logic functions between registers is assumed to be equal, and chip speed is therefore limited by whichever logic function on a chip is slowest. Since clock concurrent optimisation builds clocks simultaneously with optimising logic, the time available for logic functions need not be the same and can be varied by individually controlling when clock signals arrive at registers. Using clock concurrent optimisation, chip speed becomes limited by whichever "chain" of logic functions is slowest, where these chains break only when they reach an input to, or an output from, a chip or when they loop back on themselves. It is the explicit minimisation of critical logic chains, as opposed to critical logic paths, which most differentiates clock concurrent optimisation from traditional physical optimisation.

Commenting on Rubix, Paul Cunningham, Azuro's co-founder and CEO said, "Clock concurrent optimisation is the right way to address the crippling pre- to post-CTS timing gap which has emerged in design flows today."

Rubix is in limited availability to select Azuro customers, with general availability scheduled for April.

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