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Using DLL phase offset in FPGAs

Posted: 24 Feb 2009     Print Version  Bookmark and Share

Keywords:delay-locked loop  Stratix II  HardCopy II 

This application note by Altera describes how to implement the delay-locked loop (DLL) phase offset feature with Altera Stratix II and HardCopy II devices. A DLL provides a process, voltage, and temperature xcompensated delay that is used to phase shift the read clock from an external memory to align it with the centre of the data valid window. The DLL phase offset feature provides a method to make fine non-PVT-compensated phase adjustments to the read clock from an external memory. If the circuit board or memory timing specifications are different than expected, you can use the DLL phase offset feature to optimise the read capture timing.

View the PDF document for more information.

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