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Eliminate problems in SerDes design

Posted: 23 Feb 2009     Print Version  Bookmark and Share

Keywords:SerDes  power dissipation  system designers 

Many IC designers wake up at night with nightmares involving mixed-signal design. A classic example involves the design of high-speed serialisers and deserialisers (SerDes). If a process is selected which will allow good performance on the analogue sections of the design—for example phase locked loops, cable drivers, and very high-speed sections—then there is invariably a compromise in cost and power when it comes to the digital section.

Meanwhile, if a process is selected with an eye to low cost and low power dissipation, then the resulting small transistors struggle to meet analogue requirements. If IC designers don't do a good job of their task, then the nightmares are passed on to the equipment and system designers.

One way to avoid these nightmares is to partition the task in such a way that the bulk of the analogue tasks are housed on one chip manufactured in a process optimised for analogue performance. Digital functions, meanwhile, should be placed on a different piece of silicon.

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