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Implement QDRII+ and QDRII SRAM interfaces in FPGAs

Posted: 17 Feb 2009     Print Version  Bookmark and Share

Keywords:QDRII SRAM  Stratix III  buffer memory 

According to Altera, QDRII+ and the QDRII SRAM devices are suited for bandwidth-intensive and low-latency applications such as controller buffer memory, look-up tables, and linked lists. QDRII+ and QDRII SRAM memory architecture features separate read and write ports operating twice per clock cycle to deliver a total of four data transfers per cycle.

Stratix III and Stratix IV I/Os are designed to support double-data rate external memory standards such as the QDRII+ and QDRII SRAM. Combined with the a self-calibrating physical interface, the ALTMEMPHY megafunction, Stratix III and Stratix IV devices deliver performance of up to 400 MHz or 1.6Gbps on top and bottom I/O banks. This application note lists the maximum clock rate support for Stratix III devices interfacing with QDRII+ and QDRII SRAM devices.

View the PDF document for more information.

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