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Bring-up guide for MPC8548E PowerQUICC III

Posted: 10 Feb 2009     Print Version  Bookmark and Share

Keywords:MPC8548E  PowerQUICC III  communications processors 

This document by Freescale provides recommendations for new designs based on the MPC8548E PowerQUICC III family of integrated host communications processors. This document may also be useful in debugging newly designed systems by highlighting those aspects of a design that merit special attention during initial system start-up.

This section document outlines recommendations to simplify the first phase of design. Before designing a system with a MPC8548E device, it is recommended that the designer be familiar with the available documentation, software, models, and tools.

According to Freescale, MPC8548E features the boot sequencer to allow configuration of any memory-mapped register before the completion of power-on reset. The register data to be changed is stored in an I2C EEPROM. MPC8548E requires a particular data format for register changes as outlined in the MPC8548ERM. The boot sequencer tool is a C-code file. When compiled and given a sample data file, it generates the appropriate raw data format as outlined in the MPC8548ERM (that is, an s-record file that can be used to program the EEPROM.)

View the PDF document for more information.

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