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Effect of clock jitter on high-speed ADCs

Posted: 06 Feb 2009     Print Version  Bookmark and Share

Keywords:resolution  ADC  SFDR 

Digitizing high-speed signals to a high resolution requires careful selection of a clock that will not compromise the sampling performance of the analogue-to-digital converter (ADC). This article will give you a better understanding of clock jitter and how it affects the performance of the high-speed ADC.

As an example, LTC2209 16-bit, 160 Msps is used. This converter exhibits a signal-to-noise ratio (SNR) of 77.4 dB, with 100 dB spur free dynamic range (SFDR) throughout much of the base band region. Like most ADCs on the market today, the LTC2209 uses a sample-and-hold (S&H) circuit that essentially takes a snapshot of the ADC input at an instant in time. When the S&H switch is closed, the network at the input of the ADC is connected to the sample capacitor. At the instant the switch is opened, one-half clock cycle later, the voltage on the capacitor is recorded and held.

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