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EE Times-India > EDA/IP

Joint research aims to reduce chip size by 10x

Posted: 30 Jan 2009     Print Version  Bookmark and Share

Keywords:interconnect  packaging  research  chip footprint 

Georgia Tech and Semiconductor Research Corporation (SRC), a university-based research consortium for semiconductors and related technologies, have announced a Rs.12.51 crore ($2.5 million) collaboration among academia, industry and government to launch the Interconnect and Packaging Centre (IPC) at Georgia Tech. Joint research will be conducted at the IPC, aiming to reduce chip footprint by a factor of 10 while lowering power consumption and improving performance.

The cooperative work of the centre's participants is aimed at two objectives: creation of leading-edge technologies that connect billions of transistors on a chip, called interconnects, as well as improved ability of different chips to communicate with each other through enhanced packaging. Smaller, more powerful chips could be gained from such advancements.

"Transistors have made enormous progress in speed, performance, and miniaturisation, which places greater demand on the electrical connections between transistors, and between individual chips. The interconnect and packaging challenges are greater today than ever," said Dr. Paul Kohl, director for the IPC.

To facilitate huge computing gains, about half of the IPC research will focus on new 3D technology. 3D can provide the semiconductor industry with viable options for stacking multiple chips vertically at room temperature while maintaining millions of inter-die electrical connections.

"The 3D approach to packaging is one of the most promising options for improving functionality and performance to help ensure the continued success of the semiconductor industry," according to Dr. Scott List, director of Interconnect and Packaging Sciences for SRC-GRC, an SRC entity dedicated to extending the future of CMOS. "The year 2009 is clearly a very difficult time for the industry but continued sharing of research dollars provides a strong prescription for a brighter future."

The Interconnect and Packaging Centre begins immediate annual funding of Rs.4.10 crore ($820,000) across its eight selected programmes at Georgia Tech, Harvard, The University of Texas at Austin, Iowa State University, and Nanyang Technological University (NTU). The international participation from Singapore's NTU marks a growing trend towards acceleration of progress through integration of the best global research.

SRC is providing Rs.2.50 crore ($500,000) per year to IPC for three years. The State of Georgia is providing Rs.1.60 crore ($320,000) for each of three years. The IPC will be based in the new Marcus Nanotechnology Building at Georgia Tech.

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