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40G/100G Receiver reference design rolls

Posted: 22 Jan 2009     Print Version  Bookmark and Share

Keywords:reference design  high speed protocols  production testing  28G test 

Inphi Corp. has announced the availability of a 28G Bit Error Ratio (BER) Receiver reference design for R&D or production testing of emerging high speed protocols from 13Gbps to 28Gbps, including 100Gbit Ethernet, 40G differential quadrate phase shift keying (DQPSK), 14G Fibre Channel, and 100G dual-polarisation QPSK (DP-QPSK). Inphi says the reference design helps to accelerate time-to-market for test and measurement vendors designing next generation 28G test platforms.

For high speed data links, BER testing (BERT) is the most fundamental test at the PHY, as it measures whether the data bits are correctly transmitted across the link. BERT systems for speeds up to 12.5Gbps are well established. However, with the emergence of networking standards such as 40G SONET, 100G Ethernet and 14G Fibre Channel, design and test engineers require BERTs with high speed front-ends above 12.5Gbps and up to 28Gbps.

The Inphi 28G BER Receiver reference design addresses the challenge of designing a high speed front-end at 28Gbps, and integrates an Inphi chipset in a high performance and reliable design. The reference design, together with a 12.5G BERT and a 28G high speed test pattern generator, comprise a complete 28Gbps test solution.

For test applications requiring clock recovery, the 28G BER Receiver reference design provides a buffered copy of the high speed input data stream, which can be supplied to an optional clock recovery unit to generate a recovered clock. The 28G BER Receiver reference design is based on an Inphi chipset of a 5081DX 50Gbps 1:4 demux, 25717CF 25Gbps 1:2 fanout, and 20709SE 20Gbps 2:1 selector.

The Inphi 28G BER Receiver reference design is available immediately as a reference board for evaluation.

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