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Algorithmic synthesis tools increase performance

Posted: 22 Jan 2009     Print Version  Bookmark and Share

Keywords:algorithmic synthesis  design tools  compiler 

Synfora Inc. has introduced new versions of their PICO Extreme and PICO Extreme FPGA algorithmic synthesis design tools that will achieve higher performance and smaller area than the previous generation of the tools.

PICO Extreme is an advanced optimising compiler that transforms a sequential, untimed C algorithm into highly efficient RTL, reducing design and verification time, allowing designers to find the lowest cost implementation and enabling very rapid reaction to changes in the design specification. Enhancements announced enable designers to create and analyse hardware designs more effectively, and include quality-of-results improvements in terms of area, throughput, timing and timing correlation, and user feedback improvements.

In the new version of PICO Extreme, significant advances in scheduling algorithms enable the compiler to optimise registers in a design. In a suite of 50 actual customer designs, this yielded area improvements in the range of 5 per cent to 20 per cent, with a corresponding reduction in silicon cost. Sophisticated analysis of variable loop bounds, combined with an innovative new approach to handling early exits from loops, is said to provide performance improvements in the 10 per cent-to-30 per cent range on complex designs.

Achieving high productivity on complex designs requires that synthesis tools provide the user with sophisticated analysis, feedback and debugging capabilities to understand the performance and area bottlenecks in the design. The enhancements to PICO Extreme 08.03—including those to the reporting and feedback capabilities—improve the ability to analyse throughput bottlenecks, provide greater visualisation and reporting of the hardware cost, and allow automatic detection and feedback on potential deadlock scenarios.

Using a recursive system composition methodology, PICO Extreme allows use of familiar design styles, reduces runtime and achieves unprecedented quality of results that compete with hand design. Recursive system composition is enabled by Synfora's innovative tightly coupled accelerator block technology, allowing users to designate parts of their algorithms as application-specific building blocks, which are C procedures that can be designed and verified stand-alone. The PICO Extreme compiler automatically integrates and schedules these blocks as if they were primitive computing elements.

PICO Extreme is in use at a growing number of companies for next-generation SoCs and FPGAs in video, wireless, imaging and security applications. It has been shown to achieve 30 per cent more design functionality, differentiation and power efficiency with 30 per cent less verification time, design resource commitment and silicon cost, says Synfora.

- Clive Maxfield
Programmable Logic DesignLine





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