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EE Times-India > EDA/IP

Formal verification tools roll for beginners

Posted: 21 Jan 2009     Print Version  Bookmark and Share

Keywords:verification tools  design phase  RTL syntheis  chip design 

Since the usage of formal verification tools within the chip design value chain hitherto is restricted to a small enlightened group, OneSpin Solutions GmbH hopes to bring this technique to broader acceptance. The EDA tool vendor has amended its software and packaged it in a way that supports a step-by-step approach for beginners.

At the EDS fair in Japan, OneSpin will introduce its 360MV product family, consisting of five interoperable packages. The packages enable users to approach the topic gradually and thus should help to foster acceptance for formal assertion-based verification in SoC, ASIC and FPGA design, explained Michael Siegel, product marketing director at OneSpin.

The first-level package, dubbed "360MV Inspect for autochecks," follows a "whitebox approach" and does not require any knowledge of formal verification from the user. The tool detects RTL errors in an early design phase, claimed Siegel. In addition, it supports design optimisation in that it identifies "dead" code as well as mismatches between simulation and synthesis. "The user does not need to write assertions," promised Siegel.

Five more packages with increased functionality each—and rising requirements as to the user's expertise—direct users towards OneSpin's flagship product 360MV Certify, which integrates verification planning, verification execution and automatic gap detection.

"In general, designers do not have the time necessary to disengage from productive business and learn how to handle formal verification," Siegel said. "This typically would take several months."

With the decision to implement and offer such a staged approach towards formal verification, the start-up company admits that acceptance for this technique in the market is slower than expected. However, formal verification could shorten design cycles very significantly, Siegel insisted.

"Progress within chip companies is an evolutionary process," the product marketing director said. "It took 10 years until RTL synthesis became mainstream. And similarly, it took many years until equivalence checking and ESL were generally accepted, but it always was very clear that these techniques offer advantages in chip design," he added, hinting that formal verification currently is hitting the same obstacles as other design automation tools in the past.

"We see that formal verification is established. The discussions do no longer deal if formal verification is a useful thing but how one can use it. For this reason, we want to offer a gradual access to this technique," Siegel said.

- Christoph Hammerschmidt
EE Times Europe

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