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Measure quality in semiconductor IP

Posted: 13 Jan 2009     Print Version  Bookmark and Share

Keywords:semiconductor IP  RTL  clock synchronisation 

Most semiconductor IP today is delivered as soft IP-register transfer level (RTL) or configurable generators that produce RTL. IP suppliers do ensure correct functional behaviour. Often overlooked in this process is the communication of design intent and implementation feasibility, a task left for the IP consumer to deal with. A poorly designed IP can result in failures at the SoC level with timing, routing congestion, power, clock synchronisation, test coverage, etc. Typically these issues will not be uncovered until after a significant engineering effort has been spent on integration of the IP into the SoC and subsequent implementation. The net result is expensive design iterations, project delays and potential silicon failure.

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