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Interface direct RF synthesis DAC to FPGA

Posted: 06 Jan 2009     Print Version  Bookmark and Share

Keywords:MAX5881  DAC  Virtex-5 

This application note by Maxim discusses techniques for interfacing the MAX5881, a 4.3Gsps cable downstream direct RF synthesis DAC, to FPGAs. The focus is on the timing of the MAX5881's high-speed, digital input data interface to a Xilinx Virtex-5 FPGA. However, the techniques outlined here are also applicable to a wide variety of FPGAs and custom ASICs.

Due to the wide bandwidth of the MAX5881 4.3Gsps cable downstream direct RF synthesis DAC, its data interface requires operation at higher frequencies than lower bandwidth DACs. Designing higher bandwidth data interfaces generally requires more attention to ensure robust, error-free operation.

View the PDF document for more information.

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