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ISR design with multi-core processors

Posted: 25 Aug 2008     Print Version  Bookmark and Share

Keywords:multi-core processors  ISR  CPU  network processor 

The multi-core embedded processor shows tremendous promise as an engine for powering ISR and other multi-service gateways. Quite a few multi-core processors are on the market, and more will be available soon. Below are a few ideas for designers to consider when choosing the right SoC:

-CPU cores must use cycles to communicate and work together. The cores compete for—and can be bottlenecked by—system resources, such as bus and memory bandwidth. The more cores in use, the greater the overhead. Sooner or later, the point of diminishing returns is reached. A sophisticated core is particularly important in complex tasks that cannot be easily serialised and distributed to multiple cores. This includes control code and, to some extent, work involving content data paths. Designers can use efficient cores, having high clock rates and high instruction-per-clock counts, to perform these sorts of tasks.

-The cache sub-system has a tremendous effect on system performance. In general, the more complex the code (as in the control path and content data path in ISRs) and the greater the number of packet flows being processed (as in high-performance ISRs), the larger the cache required. Choosing the best cache size for a certain application minimises cache misses that can slow the system tremendously. (Most embedded multi-core processors have two or three levels of cache to minimise cache misses.)

-To achieve high system performance, the interconnection between I/O, memory and processing sub-systems must not cause a system bottleneck; instead, parallel processing must be maximised via the CPU cores. The interconnection bandwidth must be sufficient to satisfy the high data movement requirements of the ISR; low latency in accessing memory (for the cache and other processing elements) in the SoC can be just as important. If latency is high, a CPU core may spin its wheels for a long time before the data it needs arrives for processing.

-To select the right accelerator, you must determine whether the accelerator supports regex. Also find out whether it allows for fast, live, incremental signature updating, and whether it can go to external memory every byte while it scans. This translates into using expensive low-latency memory if performance is essential. It can also introduce contention while trying to access external memory, bringing about indeterminacy in performance.

-Supporting single-pass encryption and hashing improves performance. Selecting the right software to bring out the performance of the hardware is vital.

-ISRs are complex. The time and effort required for development of all their functions at the required performance level is far from trivial. Functional and cycle-accurate simulators will help a great deal in speeding up software development, including experimenting with different software architectures to maximise performance before and after the SoC is available. Similarly, built-in debug tools and performance monitors will help debug and optimise performance on the SoC itself.

Multicore processor technology is still moving forward, quickly, but software development on multi-core processors isn't quite there yet. Designers must select the right multi-core processor carefully to minimise development time and maximise system performance.

- Mike Hui
Freescale Semiconductor, Inc.


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