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AMD moves to 45-nm with Shanghai

Posted: 26 Dec 2008     Print Version  Bookmark and Share

Keywords:45-nm  server chip  processor  Barcelona processor 

AMD's goal was to shrink the physical dimensions and increase performance. Scaling transistors mean better performance, but most of the dimensional scaling at 45 nm is related to gate and metal pitches rather than the length of the transistor's gate or channel. The minimum gate length on Shanghai is 38 nm—a reduction of only seven per cent from the 65-nm node. But the transistor performance is 19 per cent better for the nFET and 23 per cent better for the pFET compared to 65-nm transistors. So how was this achieved?

Optimised process
The answer is optimisation. AMD improved transistor performance by squeezing every last drop out of the performance-enhancing structures that were already in use at 65 nm. The starting point was a silicon-on-insulator (SOI) wafer as opposed to bulk wafer technology used elsewhere. The rest of the transistor performance story relates to strain engineering.

For nFETs, stress memorisation stretches the n-channel first, which is enhanced later in the process flow by the addition of a nitride tensile stress liner. The liner itself is scaled down at 45 nm to ensure the required strain is adequately supplied to the transistor channel to enhance electron mobility and subsequently increase the drive current. The gate stack design is modified as well with a new sidewall spacer design for 45 nm.

The pFET performance improvement is more dramatic with drive current up to 660 �A/�m compared to 510 �A/�m on 65-nm transistors. Again, this increased output current is the result of optimised compressive strain for the p-channel device. The new pFET design moves the embedded silicon-germanium source/drain regions closer to the channel-reducing the space by half-to maximise the transfer of stress thereby increasing hole mobility. Although shorter gate lengths are not driving the improvements, it is a reduction in dimensions that is allowing increased channel stress to provide the performance scaling.

The transistor drive current for AMD's 45-nm devices is much lower than the Intel HKMG transistors. But power consumption is quickly becoming a high priority for server chips. Our transistor benchmarking indicates that leakage current is less than one-third of AMD's 65-nm process. It's also significantly lower than the Intel 45-nm HKMG process. In fact, the Ion/Ioff ratio for AMD's pFET is nearly 10 times better than the Intel pFET.

Of course, controlling power consumption at the chip level goes beyond the transistor level with clock speed reduction or even powering down whole blocks of the IC.

Architecture and process technology are by no means the only considerations when selecting a microprocessor for a server box. Upgrade path, power consumption and the interaction with chipsets and software all come into play. However, it's clear that competition is driving innovation resulting in better products and more choices.

With a major architectural overhaul, Intel will be pushing server performance with its Nehalem chips, but AMD can maintain its "negawatt" lead with its power-saving transistor design.

- Don Scansen
Semiconductor Insights

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