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Improve SI in high density FPGA-based designs

Posted: 29 Dec 2008     Print Version  Bookmark and Share


Platform verification boards typically have multiple FPGAs and hundreds of signals that are either terminated or non-terminated running between them. Checking the connectivity and locating fabrication and assembly faults becomes a must before the actual bitstream is loaded on the FPGAs for verification.

Signals that run from one FPGA to another can be series terminated, while signals running between multiple FPGAs can be parallel-terminated. Series termination is provided using resistor networks, (eight in one package each of 0402 footprint) and parallel termination using individual resistors.

This article presents an approach that helps generate a Verilog test code, and detect assembly and fabrication-related faults.

View the PDF document for more information.

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