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Understanding DDR-XAUI's feasibility

Posted: 19 Dec 2008     Print Version  Bookmark and Share

Keywords:DDR-XAUI  10 Gigabit Ethernet  XFI 

High levels of integration dictate that large numbers of XAUI interfaces must be integrated in silicon to a level where silicon devices are bound by their external interface limitations rather then their internal bandwidth. In order to minimise the number of SerDes lanes, higher speed lanes are required. The options available today are 6.25Gbps and 10Gbps (XFI) lanes. XAUI is an important compatibility interface for 10 Gigabit Ethernet component and system implementers. It provides the low pin-count and long board trace lengths that system vendors need to drive down port costs. This article argues that there is a strong business case for DDR-XAUI, a two lane 6.25Gbps XAUI in addition to XFI.

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