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UMC validates high-k process at 45nm

Posted: 27 Nov 2008     Print Version  Bookmark and Share

Keywords:high-k process  45nm node  circuit leakage power  immersion lithography 

United Microelectronics Corp. has validated its high-k metal gate process with a test SRAM design run at the 45nm node. The move is one step towards the company's goal of offering a high-k process at the 32nm node in 2010.

Intel Corp. claims it is seeing significant increases in performance and reductions in circuit leakage power with a high-k process it has in production at 45nm today using dry lithography. Rivals IBM Corp. and Advanced Micro Devices—process technology partners with UMC—have delivered immersion lithography at 45nm but will not have high-k metal gates available until the 32nm node.

UMC's archrival, neighbouring TSMC in Hsinchu, Taiwan, announced it will not deliver a high-k metal gate capability until its 28nm node. TSMC is treating its 32nm node as a half-step shrink of its 40nm node.

"With our recent achievement of working 28nm SRAM, coupled with this latest high-k process material validation, we are well positioned to offer customers a strong technology platform solution when our 32/28nm technology becomes available in 2010," said S.C. Chien, vice president of advanced technology development at UMC in a press statement.

The foundry made a working 28nm SRAM in October. It used a so-called low leakage process with double-patterning immersion lithography and strained silicon in a conventional silicon gate/silicon-oxy-nitride gate oxide technology that does not use high-k materials.

UMC said its low leakage process is targeted at portable applications such as mobile phone ICs, while the high-k process is primarily aimed at high speed products such as graphics, application processors and high-speed communication ICs. The high-k option can also be customised for 32/28nm low power applications to address individual customer requirements, the company said.

-EE Times

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