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ICs answer H.264/AVC compression issues

Posted: 26 Nov 2008     Print Version  Bookmark and Share

Keywords:H.264/AVC  analogue video  coding control  digital TV 

From digital TVs to portable electronics, the H.264/AVC next-generation video compression standard is becoming mainstream. Major processor makers—mainly Japan-based firms—are leadingthat trend with chips that not only offer higher integration at lower cost and power, but aim to resolve encoding complexities and coding control challenges facing design engineers.

With the ability to achieve more than twice the compression ratio of the existing MPEG-2 standard, H.264/AVC is indeed a major advance in bringing better-quality video to electronics. The processor market is preparing to supply full-production SoCs that support the H.264/AVC standard. Though they may offer different functions and features, they all promise to deliver one thing: crisper video.

Japan-based Fujitsu, NEC Electronics, Renesas Technology and Sigma Designs are going strong in this sector, as are major U.S. chip companies, such as Broadcom, that are also looking to bring advanced functionality and differentiated features to digital TV designs.

In an effort to help OEMs quickly develop full-HD digital TVs with H.264/AVC compatibility at low cost, NEC has developed the EMMA3TL image processing SoC with a built-in analogue A/V switch (for switching analogue input signals when multiple devices are connected), high-speed video A/D converter, audio A/D converter, analogue audio stereo decoder, HDMI receiver, audio D/A converter, USB host controller and an Ethernet controller.

The chip is the successor to NEC's EMMA2TH/H's image-processing circuit. In addition to integrating many of its predecessor's external I/O functions into its latest device, NEC also improved the image-processing circuit, enabling it to display high-resolution video as well as PC content. The colour representation was upgraded from the conventional YUV 4:2:2 format to the YUV 4:4:4 format, doubling the accuracy of its colour space, and enabling crisp image quality without smudging or blurring.

The performance of the deinterlacer and noise-reduction circuit was also improved. For analogue video input, the technology NEC developed in the existingµPD64017 3D Y/C separation chip was enhanced, and the EMMA3TL now boasts an even higher-quality analogue video decoder, supporting PAL, SECAM and NTSC.

The EMMA3TL uses a high-performance dual-core MIPS CPU capable of 1,000 DMIPS (Dhrystone MIPS), making it possible to implement networks and other apps with heavy processing loads.

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