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Designing NAND flash memory sub-systems

Posted: 24 Nov 2008     Print Version  Bookmark and Share

Keywords:NAND flash  NAND controllers  memory sub-system  discrete solution 

A variety of NAND flash architectures, the constant migration to newer, more advanced process technologies and the continual introduction of new functions have converged to make the design of NAND flash memory sub-systems tougher than ever.

The current situation in the NAND flash market presents designers with three options. They can build their own discrete solutions using flash controllers and separate NAND devices. They can use embedded NAND controllers (within chipsets/processors) along with separate NAND devices. Or they can opt to buy managed NAND solutions that offer the entire NAND memory sub-system in a pre-packaged solution.

Choices present problems
The expansion of the NAND flash market has attracted a variety of suppliers; each offering its own technology advances. For example, as device densities passed 4Gbit, NAND flash manufacturers found the traditional 512byte programming page no longer offered an optimal segmentation for programming. Many suppliers instead moved to a 2KB page size.

More recently, manufacturers started shipping a larger 4KB page size in volume. Furthermore, 8KB page size is now being offered in latest 40nm technology. At the same time, in an attempt to increase capacity, manufacturers have moved from single-level cell (SLC) to multi-level cell (MLC) architectures, which store as many as 4bits per cell.

Further complicating the problem, competing flash memory IC suppliers are constantly adding new functionality such as read caches, write caches, copy back and multiplane programming functionality. While these new features and architectural enhancements were intended to improve performance, they present inherent compatibility problems for OEMs looking to minimise inventory risk by sourcing NAND flash from multiple suppliers. Incompatibility issues also arise because of the fact that NAND flash from different vendors may have different erase and program timing requirements.

NAND controllers addressed this problem by offering a simple, standardised interface between the host system and a block of flash memory regardless of the source. In a discrete solution, OEMs typically purchase controllers and NAND memory ICs from different suppliers and then mount the devices on a board. Once the system powers up, a flash file system in the controller recognises the memory devices, executes all necessary handshaking routines for flash media support and performs low-level formatting.

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