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Automotive MCU based on Cortex-R4F processors

Posted: 07 Nov 2008     Print Version  Bookmark and Share

Keywords:automotive MCU  ARM Cortex-R4F  floating point  dual-core 


Texas Instruments Inc. introduced what it touts as the industry's first ARM Cortex-R4F processor-based floating point, lock step dual-core automotive MCU. Based on two Cortex-R4F processors, the TMS570F MCUs were designed specifically for applications required to meet the International Electrotechnical Commission (IEC) 61508 SIL3 or ISO26262 ASIL D safety standards.

"According to Strategy Analytics, the number of microcontrollers per car is forecast to double by 2012," said Wayne Lyons, Director, Embedded Solutions, ARM. "Added to this growth, the sophistication of safety control functions is expected to increase substantially. TI's Cortex-R4F processor-based TMS570F MCUs offer designers a way to reduce that complexity while offering top-notch performance and the ability to differentiate their solutions."

Using the TMS570F MCU, developers can now eliminate the weeks—and often months—of time spent contending with scaling, saturation and adjustment of numerical resolution required in fixed point implementations. The dual core lockstep implementation also simplifies software development by removing redundant safety system requirements.

Hardware built in self test (BIST) of both memory and CPU functions further increases integration and lets designers detect latent defects without using complex safety software drivers that reduce performance and have significant code size overhead. Hardware comparison of the CPU's outputs provides on line diagnostics with exceptional safety response time and no additional software overhead.

The Cortex-R4F processor-based MCU is designed to meet error-free automotive safety standards and provide system-wide protection through seamless support for error detection from the processor, through the interconnect and into the memories.

The error correction code (ECC) logic is integrated into the Cortex-R4F CPU, which protects both the memories and busses. Because ECC is evaluated within the CPU, the system takes advantage of the eight-stage pipeline to allow time for ECC evaluation with no performance impact. In the event of a memory error, the ECC logic will correct it, rather than just communicating the error and stopping the system.

Industry standard peripherals include FlexRay protocol controller, up to three CAN and two LIN modules along with TI's high-end timer co-processor and two 12-bit analogue to digital converters (ADC). Targeted applications include chassis control, braking, electronic vehicle stability and steering as well as advanced driver assistance with higher and lower memory and performance variations in development.

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