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ADC achieves power savings

Posted: 03 Nov 2008     Print Version  Bookmark and Share

Keywords:ADC  power savings  low power portability 

LTC2261

Linear Technology has introduced a low-power 14bit, 125Msps ADC that dissipates only 127mW, less than one-third the power of prior solutions.

Operating from a low 1.8V analogue supply, the LTC2261 achieves significant power savings without sacrificing AC performance. This ADC offers signal to noise ratio (SNR) performance of 73.4dB and spurious free dynamic range (SFDR) of 85dB at base band. Ultra low jitter of 0.17psRMS allows undersampling of IF frequencies with excellent noise performance.

The combination of low power and good AC performance provide a much needed power savings to battery powered portable instrumentation and multi-channel systems such as medical ultrasound and non-destructive test equipment. JTRS software defined radios and other portable communication equipment will also benefit from the low power portability of this breakthrough ADC family.

The LTC2261 eases the task of designing with high speed ADCs, says Linear. In such designs care is needed when routing digital outputs to avoid digital noise coupling back and distorting the analogue reading. Interference from digital feedback is visible as unwanted tones in the ADC output spectrum. To help negate this effect, the LTC2261 offers a data randomiser to randomise the digital output before it is transmitted to achieve a significant reduction in unwanted tone amplitude by spreading this energy into the noise floor. Using this data encoding scheme can reduce the residual tones caused by digital feedback by 10-15dB.

The LTC2261's digital outputs can be set to full rate CMOS, double data rate CMOS, or double data rate LVDS. Double data rate digital outputs allow data to be transmitted on both the rising edge and the falling edge of the clock, reducing the number of data lines needed by half. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.

Offered in a 6mm x 6mm QFN package, the LTC2261 includes a clock duty cycle stabiliser circuit to facilitate non-50 per cent clock duty cycles, programmable digital output timing, programmable LVDS output current and optional LVDS output termination. These features combine to make the data transmission between the ADC and the microcontroller more flexible.

The LTC2261 family comprises six pin-compatible members, offering 14bit resolution at 125Msps, 105Msps and 80Msps and 12bit resolution at 125Msps, 105Msps and 80Msps, with full production planned for December 2008.





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